2fah-c20r series - integrated passive & active device using csp specifications are subject to change without notice. customers should verify actual device performance in their specific applications. solder bumps silicon die electrical characteristics symbol minimum nominal maximum unit (t a = 25 ? unless otherwise noted) zener diode breakdown voltage @ 1 ma v br 67.28 v leakage current @ 3 v i r 1 ? esd performance (note 1) withstand contact discharge ? kv air discharge ?5 kv let through (note 2) contact discharge ?50 v air discharge ?50 v channel specification resistance r 90 100 110 ? capacitance @ 1 v & 1 mhz c 8.5 10.5 12.5 pf thermal characteristics (t a = 25 ? unless otherwise noted) operating temperature t j -40 25 +85 ? storage temperature t stg -60 25 +125 ? total power dissipation @ 70 ? p d 100 mw general information electrical & thermal characteristics this application specific integrated passive component is designed to provide all of the necessary esd protection and line resistance required on the data port of a custom portable electronic device. the esd protection provided by the component enables the data port to withstand ? kv contact / ?5 kv air discharge when tested according to the method specified in iec 61000-4-2. the component incorporates 7 identical channels and is supplied in a 20 pin csp package which is intended to be mounted directly onto an fr4 printed circuit board. this package will meet typical thermal cycle and bend test specifica- tions without the use of an underfill material. note: 1. the iec 61000-4-2 test method will be adapted for component level testing. the device will provide the specified esd pro tection performance on the in 1-7 pins only. 2. let through is a measure of the component of an incident esd transient that the protection device allows through to the do wn stream circuitry. figure 1 C csp format features lead free versions available rohs compliant (lead free version)* new product development integrated passive device esd protection to iec61000-4-2 spec. *rohs compliant versions available *rohs directive 2002/95/ec jan 27 2003 including annex obsolete
dimensions = microns (mils) specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical characteristics 2fah-c20r series - integrated passive & active device using csp a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 c1 c2 c3 c4 c5 d1 d2 d3 d4 d5 bump a1/pin 1 indicator bourns logo 858 40 (33.78 1.57) 225 20 (8.86 0.79) 45 45 (1.78 1.78) 45 45 (1.78 1.78) 248.5 45 (9.78 1.78) 248.5 45 (9.78 1.78) 348.5 45 (13.72 1.78) 1997 45 (78.62 1.78) 2597 45 (102.24 1.78) 500 (19.69) 300 (11.81) dia. 500 (19.69) this is a silicon-based device and is packaged using chip scale packaging technology. solder bumps, formed on the silicon die, provide the interconnect medium from die to pcb. the bumps are arranged on the die in a regular grid formation. the grid pitch is 0.5mm. the dimensions for the csp packaged device are shown in fig. 2 below. reliability data exists and continues to be gathered on an ongoing basis for bourns integrated passive and active devices using csp packaging. ?ackage level?testing of the integrity of the solder joint is carried out on an independent daisy-chain test device. a 25-pin daisy chain component is available from bourns for this purpose (part number 2tad-c25r). this is a 5 x 5 array featuring 0.5mm pitch solder bumps. the distance to neutral point (dnp) on that component is larger than that of the 2fah-c20r and is thus deemed a worse case for thermal cycle testing. ?ilicon level?reliability performance will be assured by similarity to other integrated passive and active devices using csp product from bourns. fig. 2 C device mechanical drawing reliability this section contains the schematic (see fig. 3 below) for the single channel in the integrated passive device. note that the e lectrical parameters of primary interest are (a) dc resistance and (b) esd performance. in terms of dc parameters it should be noted that all resistor values have a tolerance of ?0 %. this schematic consists of a series 100ohm resistance and back to back zener 6.5 vol t diodes for esd protection. key design parameters dc channel resistance: 100 ? ?0 % dc channel capacitance: 12.5 pf maximum v br : 6 v min, 8 v max @ i br = 1 ma. i r : 1 ua max @ v r =3 v. individual channel schematic 100 ? 6.5v in out fig. 3 C channel schematic obsolete
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. 2fah-c20r series - integrated passive & active device using csp block diagram 100 ? 6.5v in1 out1 100 ? 6.5v in2 out2 100 ? 6.5v in3 out3 100 ? 6.5v in4 out4 100 ? 6.5v in5 out5 100 ? 6.5v in6 out6 100 ? 6.5v in7 out7 ground ground pin a1 location a b c d 1 2 3 4 5 fah lotcode figure 4 contains a block diagram of the csp device. this diagram includes the pin names and basic electrical connections associated with each channel. the device will be laser marked on the backside according to the following fig. 5 scheme below. position a1, on the bump grid is located at the top left of the die when the die is orientated so that the mark is read in the normal fashion. marking please consult bourns? thin film on silicon using csp users guide application note for notes on pcb design and smt processing. pcb design and smt processing fig. 4 C device block diagram fig. 5 C backside laser mark how to order 2 fah - c20r __ __ thinfilm model chipscale no. of solder bumps packaging option r = tape and reel packaged 3000 pcs. / 7 ?reel terminations lf = sn/ag/cu (lead free) blank = sn/pb obsolete
copyright? 2001, bourns, inc. litho in u.s.a. ip 5/02 .5m/cs0202 2fah-c20r rev. g, 02/05 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. 2fah-c20r series - integrated passive & active device using csp the pin-out for the device is shown in fig. 6. note also that the device is shown with bumps facing up. function pin out function pin out in1 b1 out4 d3 in2 a1 out5 d4 in3 a2 out6 d5 in4 a3 out7 c5 in5 a4 ground b2 in6 a5 ground b3 in7 b5 ground b4 out1 c1 ground c2 out2 d1 ground c3 out3 d2 ground c4 device pin out the product will be dispensed in an 8mm x 4mm tape and reel format - see fig. 7 diagram below. the tape and reel package will conform to customer specification. packaging out 2 out 3 out 4 out 5 out 1 in 1 in 2 in 3 in 4 in 5 out 6 out 7 in 7 in 6 ground x 6 12345 d c b a 2.0 0.05 (.08 .002) 0.3 0.05 (.01 .002) 2.19 0.05 (.09 .002) 2.77 0.05 (.11 .002) 1.75 0.1 (.07 .004) 3.5 0.05 (.14 .002) 8.0 0.3 (.31 .01) 0.9 0.05 (.04 .002) orientation of component in pocket backside facing up 0.3 (0.01) 4.0 0.1 (.16 .004) 4.0 0.1 (.16 .004) 0.25 (0.001) typ. r 1.5 0.1/-0 (.06 .004/-0) dia. max. r fig. 6 (a) - device pin out bumps up view fig. 6 (b) - pin listings fig. 7 - tape and reel drawing dimensions = millimeters (inches) reliable electronic solutions asia-pacific: tel +886- (0)2 25624117 ?fax +886- (0)2 25624116 europe: tel +353 214 515 225 ?fax +353 214 515 292 the americas: tel +1-951 781-5492 ?fax +1-951 781-5700 www.bourns.com obsolete
|
